1. Field of the Invention
This disclosure relates to a semiconductor integrated circuit, and more particularly, to a logic circuit capable of testing and optimizing a semiconductor integrated circuit as if fuses are not cut without being affected by fuses cut for a primary test and optimization of the semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit that has passed through a semiconductor fabrication process may pass an electrical characteristic test and a functional test while it is in a wafer state. The electrical characteristic test may measure parameters of transistors, resistors and capacitors using test patterns of the semiconductor integrated circuit. The functional test tests the operation of the semiconductor integrated circuit. The internal logic scheme of the semiconductor integrated circuit may be changed or a delay time controlled to optimize the operation of the semiconductor integrated circuit based on the electrical characteristic test and functional test results.
A method of changing the internal logic scheme or controlling the delay time is carried out through a fuse test logic circuit including fuses. The fuse test logic circuit is part of the semiconductor integrated circuit. The fuse test logic circuit selectively cuts the fuses and changes the internal logic scheme or controls the delay time in response to the cut fuses.
FIG. 1 is a circuit diagram of a conventional fuse test logic circuit 100. Referring to FIG. 1, the fuse test logic circuit 100 includes a PMOS transistor 101, a fuse 102, and an NMOS transistor 103, which are serially connected between a power supply voltage VDD and a ground voltage VSS. The gates of the PMOS transistor 101 and NMOS transistor 103 receive a power stabilizing signal PVCCHB. The power stabilizing signal PVCCHB transitions from a logic high level to a logic low level when the operating power of a semiconductor integrated circuit including the logic circuit 100 has stabilized.
The fuse test logic circuit 100 further includes a first inverter 104 connected to a node NA between the fuse 102 and the NMOS transistor 103, a NOR gate 105 receiving the output signal of the first inverter 104 and a TMRS pointer TMRS, and a second inverter 106 receiving the output signal of the NOR gate 105 and outputting a fuse test on signal Fuse_Test_ON. The TMRS pointer TMRS is a test signal set in a mode register MRS in a test mode. The fuse test on signal Fuse_Test_ON having a logic high level is generated when the TMRS pointer TMRS has a logic high level.
The fuse test logic circuit 100 determines the logic level of the fuse test on signal Fuse_Test_ON in response to the output signal of the first inverter 104 and the TMRS pointer TMRS, inputted to the NOR gate 105. The output signal of the first inverter 104 is determined in response to whether the fuse 102 is cut and the power stabilizing signal PVCCHB having a logic low level. The output signal of the first inverter 104 has a logic low level when the fuse 102 is not cut and has a logic high level when the fuse 102 is cut. As a result, the fuse test on signal Fuse_Test_ON has a logic high level when the TMRS pointer TMRS has a logic high level when the fuse 102 is not cut, and has a logic high level when the output signal of the first inverter 104 has a logic high level when the fuse 100 is cut. The fuse test on signal Fuse_Test_ON at a logic high level serves as a control signal for changing the internal logic scheme of the semiconductor integrated circuit or controlling delay time.
The semiconductor integrated circuit including the fuse test logic circuit 100 can judge that there is a need to change the internal logic scheme or control delay time in response to the results of tests carried out on the semiconductor integrated circuit while it is in a wafer state. Then, the fuse test logic circuit 100 selectively cuts the fuse 102 to generate the fuse test on signal Fuse_Test_ON having a logic high level. The fuse test on signal Fuse_Test_ON at a logic high level changes the internal logic scheme of the semiconductor integrated circuit or controls the delay time while the semiconductor integrated circuit in a wafer state is tested.
The semiconductor integrated circuit that has been tested in its wafer state is tested again after being packaged. The fuse test logic circuit 100 having the cut fuse 102 in the wafer state generates the fuse test on signal Fuse_Test_ON having a logic high level all the time while a package test of the semiconductor integrated circuit is performed. That is, the fuse test on signal Fuse_Test_ON at a logic high level, which is set to change the internal logic scheme of the semiconductor integrated circuit or control the delay time in response to the wafer test result, is also applied to the package test. Accordingly, the package test is performed on the semiconductor integrated circuit having the changed internal logic scheme or controlled delay time.
However, even though the fuse 102 was cut in response to the wafer test result to change the internal logic scheme or control the delay time such that the operation of the semiconductor integrated circuit was optimized, there is often a need to carry out the package test while the fuse 102 is not cut, that is, the internal logic scheme of the semiconductor integrated circuit is not varied or the delay time is not controlled. This is because of the variation of environmental parameters during the test of a packaged semiconductor integrated circuit may result in a situation in which the optimization condition of the semiconductor integrated circuit should be re-set. For this, there is a need to perform the package test while the fuse 102 is not cut.
When the fuse test logic circuit 100 cuts the fuse 102 once during the wafer test, information about the cut fuse continuously affects the circuit through the package test. Thus, a semiconductor integrated circuit having a fuse test logic circuit 100 with an uncut fuse 102 should be manufactured again if the circuit having no cut fuse is needed. Accordingly, a long period of time is taken to optimize the semiconductor integrated circuit due to the time required for the semiconductor fabrication process.